A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing


HeteroCL is a programming infrastructure composed of a Python-based domain-specific language (DSL) and a compilation flow. The HeteroCL DSL provides a clean abstraction that decouples algorithm specification from three important types of hardware customization in compute, data types, and memory architectures. HeteroCL further captures the interdependence among these techniques, allowing programmers to explore various trade-offs in a systematic and productive manner. In addition, our framework produces highly efficient hardware implementations for a variety of popular workloads by targeting spatial architecture templates such as systolic arrays and stencil with dataflow architectures.

Why HeteroCL

Productive Environment

HeteroCL provides a clean abstraction that decouples the algorithm specification from hardware customization, which allows programmers to explore various trade-offs and interdependence in a productive and systematic manner.

Flexible Programming

HeteroCL nicely blends declarative symbolic expressions with imperative code. It also provides a unified interface to specify customization schemes for both programs. This allows HeteroCL to support a broad range of applications.

Efficient Architecture

HeteroCL produces highly efficient spatial architectures by incorporating state-of-the-art HLS optimizations such as PolySA for systolic arrays and SODA for stencil with dataflow architectures. This allows productive and effective acceleration of many popular workloads.

Heterogenous Back-End

HeteroCL provides a fully automated compilation flow from a HeteroCL program to heterogeneous compute platforms integrating CPUs and FPGAs. Our compiler generates LLVM code on CPUs and HLS code for FPGA targets.

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Key Features

Bit-Accurate Data Types

HeteroCL supports arbitrary-precision integers and fixed-point nubmers. It further decouples quantization schemes from the algorithm, allowing efficient design space exploration.

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Data Reuse Schemes

HeteroCL allows programmers to specify data reuse buffers such as linebuffers and window buffers in a user-defined sequence, which is common in many workloads such as image processing and machine learning.

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Macros for Spatial Architectures

HeteroCL provides macros that map to highly efficient spatial architecture templates, which saves programmers from writing a convoluted combination of different types of hardware customization..

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Embedded Imperative DSL

With imperative programming, programmers can fine-tune their algorithms. With embedded DSL, every program is gauranteed to be synthesizable on the specified targets.

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Want to know more about HeteroCL?

Learn more about HeteroCL by reading our FPGA 2019 publication or the documentation.

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